ST SPC560P34 User Manual

FlexCAN RM0046
544/936 Doc ID 16912 Rev 5
5
WAK_MSK
Wake Up Interrupt Mask
This bit enables the Wake Up Interrupt generation.
0 Wake Up Interrupt is disabled.
1 Wake Up Interrupt is enabled.
6
SOFT_RST
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory
mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR,
ESR, IMASK1, IFLAG1. Configuration registers that control the interface to the CAN bus are not
affected by soft reset. The following registers are unaffected:
–CTRL
– RXIMR0–RXIMR31
– RXGMASK, RX14MASK, RX15MASK
– all Message Buffers
The SOFT_RST bit can be asserted directly by the CPU when it writes to the MCR, but it is also
asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and
has to follow a request/acknowledge procedure across clock domains, it may take some time to
fully propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is
automatically negated when reset completes. Therefore, software can poll this bit to know when
the soft reset has completed.
Soft reset cannot be applied while clocks are shut down in any of the low power modes. The
module should be first removed from low power mode, and then soft reset can be applied.
0 No reset request.
1 Resets the registers marked as “affected by soft reset” in Tabl e 2 64 .
7
FRZ_ACK
Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler is stopped. The
Freeze mode request cannot be granted until current transmission or reception processes have
finished. Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually
entered Freeze Mode. If Freeze mode request is negated, then this bit is negated once the
FlexCAN prescaler is running again. If Freeze mode is requested while FlexCAN is in any of the
low power modes, then the FRZ_ACK bit will only be set when the low power mode is exited. See
Section , “Freeze mode for more information.
0 FlexCAN not in Freeze mode, prescaler running.
1 FlexCAN in Freeze mode, prescaler stopped.
8
SUPV
Supervisor Mode
This bit configures some of the FlexCAN registers to be either in Supervisor or Unrestricted
memory space. The registers affected by this bit are marked as S/U in the Access Type column of
Ta bl e 26 4 . The reset value of this bit is 1, so the affected registers start with Supervisor access
restrictions.
0 Affected registers are in Unrestricted memory space.
1 Affected registers are in Supervisor memory space. Any access without supervisor permission
behaves as though the access was done to an unimplemented register location.
Table 273. MCR field descriptions (continued)
Field Description

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English