RM0046 Peripheral Bridge (PBRIDGE)
Doc ID 16912 Rev 5 279/936
13 Peripheral Bridge (PBRIDGE)
13.1 Introduction
The Peripheral Bridge (PBRIDGE) is the interface between the system bus and on-chip
peripherals.
13.1.1 Block diagram
Figure 121. PBRIDGE interface
13.1.2 Overview
The PBRIDGE acts as interface between the system bus and lower bandwidth peripherals.
Accesses that fall within the address space of the PBRIDGE are decoded to provide
individual module selects for peripheral devices on the slave bus interface.
As shown in Figure 121, the asynchronous bridge is a dedicated module that
resynchronizes signals synchronous to the system clock (SYS_CLK) to the ones
synchronous to the motor control clock (MC_PLL_CLK).
The PBRIDGE has the following key features:
● Supports the slave interface signals. This interface is only meant for slave peripherals.
● Supports 32-bit slave peripherals (byte, halfword, and word reads and writes are
supported to each)
● Provides configurable per-master access protections
13.1.3 Modes of operation
The PBRIDGE has only one operating mode.
Peripheral
Bridge
System Bus
System Bus Crossbar Switch (XBAR)
Asynchronous
Bridge
eTimer_0
Other peripherals
FlexPWM
ADC_0
Safety_Port
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