ST SPC560P34 User Manual

Nexus Development Interface (NDI) RM0046
858/936 Doc ID 16912 Rev 5
36.9 Debug support overview
Internal debug support in the e200z0h core allows for software and hardware debug by
providing debug functions, such as instruction and data breakpoints and program trace
modes. For software based debugging, debug facilities consisting of a set of software
accessible debug registers and interrupt mechanisms are provided. These facilities are also
available to a hardware based debugger which communicates using a modified IEEE 1149.1
Test Access Port (TAP) controller and pin interface. When hardware debug is enabled, the
debug facilities controlled by hardware are protected from software modification.
Software debug facilities are built on Power Architecture technology. e200z0h supports a
subset of these defined facilities. In addition to the facilities built on Power Architecture
technology, e200z0h provides additional flexibility and functionality in the form of linked
instruction and data breakpoints, and sequential debug event detection. These features are
also available to a hardware-based debugger.
The e200z0h core provides support for a Nexus real-time debug module. Real-time
debugging in an e200z0h-based system is supported by a Nexus class 2, 3, or 4 module.
36.9.1 Software Debug Facilities
e200z0h provides debug facilities to enable hardware and software debug functions, such
as instruction and data breakpoints and program single stepping. The debug facilities
consist of a set of debug control registers (DBCR0–2, DBCR4, DBERC0), a set of address
compare registers (IAC1, IAC2, IAC3, IAC4, DAC1, and DAC2), a set of data value compare
registers (DVC1, DVC2), a Debug Status Register (DBSR) for enabling and recording
various kinds of debug events, and a special Debug interrupt type built into the interrupt
mechanism. The debug facilities also provide a mechanism for software-controlled
processor reset in a debug environment.
Software debug facilities are enabled by setting the internal debug mode bit in Debug
Control register 0 (DBCR0
IDM
). When internal debug mode is enabled, debug events can
occur, and can be enabled to record exceptions in the Debug Status register (DBSR). If
enabled by MSR
DE
, these recorded exceptions cause Debug interrupts to occur. When
DBCR0
IDM
is cleared, (and DBCR0
EDM
is cleared as well), no debug events occur, and no
status flags are set in DBSR unless already set. In addition, when DBCR0
IDM
is cleared (or
is overridden by DBCR0
EDM
being set and DBERC0 indicating no resource is “owned” by
software) no Debug interrupts will occur, regardless of the contents of DBSR. A software
Debug interrupt handler may access all system resources and perform necessary functions
appropriate for system debug.
Power Architecture technology compatibility
The e200z0h core implements a subset of the Power Architecture solutions internal debug
features. The following restrictions on functionality are present:
● Instruction address compares do not support compare on physical (real) addresses.
● Data address compares do not support compare on physical (real) addresses.
36.9.2 Additional Debug Facilities
In addition to the debug functionality built on Power Architecture technology, e200z0h
provides capability to link instruction and data breakpoints, and also provides a sequential
breakpoint control mechanism.

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English