ST SPC560P34 - Figure 53. DRUN Mode Configuration Register (ME_DRUN_MC)

Mode Entry Module (MC_ME) RM0046
160/936 Doc ID 16912 Rev 5
DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please refer to Table 4 6 for
details.
Note: Byte write accesses are not allowed to this register.
Figure 53. DRUN Mode Configuration Register (ME_DRUN_MC)
Address 0xC3FD_C02C Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000
PLL0ON
XOSC0ON
16 MHz_IRCON
SYSCLK
W
Reset0000000000010000