RM0046 Boot Assist Module (BAM)
Doc ID 16912 Rev 5 829/936
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Timing segment 2 is kept as large as possible to keep sample time within bit time.
Table 446. FlexCAN standard compliant bit timing segment settings
Time Segment 1 Time Segment 2 RJW
5..10 2 1..2
4..11 3 1..3
5..12 4 1..4
6..13 5 1..4
7..14 6 1..4
8..15 7 1..4
9..16 8 1..4
Table 447. Lookup table for FlexCAN bit timings
Desired number of
Time quanta (DTq)
Time Segment 2 Time segment 1
PSEG2+1 PSEG1+1 PROPSEG+1
8 to 13
(1)
1. PRESDIV+1 > 1
22DTq-5
8 to 13
(2)
2. PRESDIV+1 = 1 (to accommodate information processing time IPT of 3 tq) Note: All TSEG1 and TSEG2
times have been chosen to preserve a sample time between 70% and 85% of the bit time.
32DTq-6
14 to 15 3 3 DTq-6
16 to 17 4 4 DTq-7
18 to 19 5 5 DTq-8
20 to 21 6 6 DTq-9
22 to 23 7 7 DTq-10
24 to 25 8 8 DTq-11
Table 448. PRESDIV + 1 = 1
Desired number of time quanta Register contents for CANA_CR
8 0x004A_2001
9 0x004A_2002
10 0x004A_2003
11 0x004A_2004
12 0x004A_2005
13 0x004A_2006
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