RM0046 FlexCAN
Doc ID 16912 Rev 5 561/936
update it until the Interrupt Flag be negated by CPU. It means that the CPU must clear the
corresponding IFLAG before starting to prepare this MB for a new transmission or reception.
22.4.3 Arbitration process
The arbitration process is an algorithm executed by the MBM that scans the whole MB
memory looking for the highest priority message to be transmitted. All MBs programmed as
transmit buffers will be scanned to find the lowest ID
(a)
or the lowest MB number or the
highest priority, depending on the LBUF and LPRIO_EN bits on the Control Register. The
arbitration process is triggered in the following events:
● During the CRC field of the CAN frame
● During the error delimiter field of the CAN frame
● During Intermission, if the winner MB defined in a previous arbitration was deactivated,
or if there was no MB to transmit, but the CPU wrote to the C/S word of any MB after
the previous arbitration finished
● When MBM is in Idle or Bus Off state and the CPU writes to the C/S word of any MB
● Upon leaving Freeze Mode
When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is
transmitted first. When LBUF and LPRIO_EN are both negated, the MB with the lowest ID is
transmitted first but. If LBUF is negated and LPRIO_EN is asserted, the PRIO bits augment
the ID used during the arbitration process. With this extended ID concept, arbitration is done
based on the full 32-bit ID and the PRIO bits define which MB should be transmitted first,
therefore MBs with PRIO = 000 have higher priority. If two or more MBs have the same
priority, the regular ID will determine the priority of transmission. If two or more MBs have
the same priority (3 extra bits) and the same regular ID, the lowest MB will be transmitted
first.
Once the highest priority MB is selected, it is transferred to a temporary storage space
called Serial Message Buffer (SMB), which has the same structure as a normal MB but is
not user accessible. This operation is called “move-out” and after it is done, write access to
the corresponding MB is blocked (if the AEN bit in the MCR is asserted). The write access is
released in the following events:
● After the MB is transmitted
● FlexCAN enters in HALT or BUS OFF
● FlexCAN loses the bus arbitration or there is an error during the transmission
At the first opportunity window on the CAN bus, the message on the SMB is transmitted
according to the CAN protocol rules. FlexCAN transmits as many as 8 data bytes, even if the
DLC (Data Length Code) value is bigger.
22.4.4 Receive process
To be able to receive CAN frames into the mailbox MBs, the CPU must prepare one or more
Message Buffers for reception by executing the following steps:
1. If the MB has a pending transmission, write an ABORT code (‘1001’) to the Code field
of the Control and Status word to request an abortion of the transmission, then read
back the Code field and the IFLAG register to check if the transmission was aborted
a. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed
inside the ID at the same positions they are transmitted in the CAN frame.
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