Flash Memory RM0046
322/936 Doc ID 16912 Rev 5
phase cycle to “retry” the read reference and sends the registered information to
the array as bkn_fl_rd_en is asserted. Once the retried address phase is
complete, the read is processed normally and once the data is valid, it is
forwarded to the AHB bus and hready_out negated to terminate the system bus
transfer.
● BKn_RWWC = 0b110
– This setting is similar to the basic stall-while-write capability provided when
BKn_RWWC = 0b111 with the added ability to generate a notification interrupt if a
read arrives while the array is busy with a program/erase operation. There are two
notification interrupts, one for each bank.
● BKn_RWWC = 0b101
– Again, this setting provides the basic stall-while-write capability with the added
ability to terminate any program/erase operation if a read access is initiated. For
this setting, the read request is captured and retried as described for the basic
stall-while-write, plus the program/erase operation is terminated by the platform
Flash controller’s assertion of the bkc_fl_abort signal. The bkn_fl_abort signal
remains asserted until bkn_fl_done is driven high. For this setting, there are no
notification interrupts generated.
● BKn_RWWC = 0b100
– This setting provides the basic stall-while-write capability with the ability to
terminate any program/erase operation if a read access is initiated plus the
generation of a termination notification interrupt. For this setting, the read request
is captured and retried as described for the basic stall-while-write, the
program/erase operation is terminated by the platform Flash controller’s assertion
of the bkn_fl_abort signal and a termination notification interrupt generated. There
are two termination notification interrupts, one for each bank.
As detailed above, there are a total of four interrupt requests associated with the stall-while-
write functionality. These interrupt requests are captured as part of ECSM’s Interrupt
Register and logically summed together to form a single request to the interrupt controller.
For example timing diagrams of the stall-while-write and terminate-while-write operations,
see Figure 149 and Figure 150 respectively.
17.2.17 Wait state emulation
Emulation of other memory array timings are supported by the platform Flash controller on
read cycles to the Flash. This functionality may be useful to maintain the access timing for
blocks of memory that were used to overlay Flash blocks for the purpose of system
calibration or tuning during code development.
Table 139. Platform Flash controller stall-while-write interrupts
MIR[n] Interrupt description
ECSM.MIR[7] Platform Flash bank0 termination notification, MIR[FB0AI]
ECSM.MIR[6] Platform Flash bank0 stall notification, MIR[FB0SI]
ECSM.MIR[5] Platform Flash bank1 termination notification, MIR[FB1AI]
ECSM.MIR[4] Platform Flash bank1 stall notification, MIR[FB1S1]
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