RM0046 FlexCAN
Doc ID 16912 Rev 5 571/936
When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer
memory during the available time slot. In order to have sufficient time to do that, the
following requirements must be observed:
â—Ź A valid CAN bit timing must be programmed, as indicated in Table 287
â—Ź The peripheral clock frequency can not be smaller than the oscillator clock frequency,
that is, the PLL can not be programmed to divide down the oscillator clock
â—Ź There must be a minimum ratio between the peripheral clock frequency and the CAN
bit rate, as specified in Tabl e 2 88
A direct consequence of the first requirement is that the minimum number of time quanta per
CAN bit must be 8, so the oscillator clock frequency should be at least 8 times the CAN bit
rate. The minimum frequency ratio specified in Table 2 8 8 can be achieved by choosing a
high enough peripheral clock frequency when compared to the oscillator clock frequency, or
by adjusting one or more of the bit timing parameters (PRESDIV, PROPSEG, PSEG1,
PSEG2). As an example, taking the case of 32 MBs, if the oscillator and peripheral clock
frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per bit,
then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to 1
and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator
clock frequencies should be at least 2.
22.4.9 Modes of operation details
Freeze mode
This mode is entered by asserting the HALT bit in the MCR or when the MCU is put into
Debug Mode. In both cases it is also necessary that the FRZ bit is asserted in the MCR and
the module is not in any of the low power modes. When Freeze Mode is requested during
transmission or reception, FlexCAN does the following:
â—Ź Waits to be in either Intermission, Passive Error, Bus Off or Idle state
â—Ź Waits for all internal activities like arbitration, matching, move-in and move-out to finish
â—Ź Ignores the Rx input pin and drives the Tx pin as recessive
â—Ź Stops the prescaler, thus halting all CAN protocol activities
â—Ź Grants write access to the Error Counters Register, which is read-only in other modes
â—Ź Sets the NOT_RDY and FRZ_ACK bits in MCR
After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in the
MCR before executing any other action, otherwise FlexCAN may operate in an
unpredictable way. In Freeze mode, all memory mapped registers are accessible.
Exiting Freeze Mode is done in one of the following ways:
â—Ź CPU negates the FRZ bit in the MCR
â—Ź The MCU is removed from Debug Mode and/or the HALT bit is negated
Table 288. Minimum ratio between peripheral clock frequency and CAN bit rate
Number of message buffers Minimum ratio
16 8
32 8
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