RM0046 Periodic Interrupt Timer (PIT)
Doc ID 16912 Rev 5 785/936
Current Timer Value Register n (CVALn)
These registers indicate the current timer position.
Figure 459. Current Timer Value register n (CVALn)
Address:
Channel Base + 0x0004
CVAL0 = PIT_BASE + 0x0104
CVAL1 = PIT_BASE + 0x0114
CVAL2 = PIT_BASE + 0x0124
CVAL3 = PIT_BASE + 0x0134
Access: User read-only
0123456789101112131415
R
TVL31 TVL30 TVL29 TVL28 TVL27 TVL26 TVL25 TVL24 TVL23 TVL22 TVL21 TVL20 TVL19 TVL18 TVL17 TVL16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TVL15 TVL14 TVL13 TVL12 TVL11 TVL10
TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0
W
Reset0000000000000000
Table 420. CVALn field descriptions
Field Description
TVLn
Current Timer Value
These bits represent the current timer value. Note that the timer uses a downcounter.
NOTE: The timer values will be frozen in Debug mode if the FRZ bit is set in the PIT Module
Control Register (see Figure 457).
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