ST SPC560P34 - Fault Channel Registers; Figure 358. Fault Control Register (FCTRL); Table 357. MCTRL Field Descriptions

RM0046 FlexPWM
Doc ID 16912 Rev 5 671/936
25.6.5 Fault channel registers
Fault Control Register (FCTRL)
Table 357. MCTRL field descriptions
Field Description
0:3
IPOL[3:0]
Current Polarity
This buffered read/write bit selects between PWMA and PWMB as the source for the generation
of the complementary PWM pair output. IPOL is ignored in independent mode.
PWMB (Figure 334) generates complementary PWM pairs.
PWMA (Figure 334) generates complementary PWM pairs.
The IPOL bit does not take effect until a FORCE_OUT event takes place in the appropriate submodule.
Reading the IPOL bit reads the buffered value and not necessarily the value currently in effect.
4:7
RUN[3:0]
Run
This read/write bit enables the clocks to the PWM generator. When RUN equals zero, the
submodule counter is reset. A reset clears RUN.
0 Do not load new values.
1 PWM generator enabled.
For proper initialization of the LDOK and RUN bits, see Section 25.9.5, “Initialization.
8:11
CLDOK[3:0]
Clear Load Okay
This write only bit clears the LDOK bit. Write a 1 to this location to clear the corresponding
LDOK. If a reload occurs with LDOK set at the same time that CLDOK is written, then the reload
will not be performed and LDOK will be cleared. This bit is self clearing and always reads as a 0.
12:15
LDOK[3:0]
Load Okay
This read/set bit loads the PRSC bits of CTRL1 and the INIT, and VALx registers into a set of
buffers. The buffered prescaler divisor, submodule counter modulus value, and PWM pulse width
take effect at the next PWM reload. Set LDOK by reading it when it is logic zero and then writing
a logic one to it. The VALx, INIT, and PRSC fields cannot be written while LDOK is set. LDOK is
automatically cleared after the new values are loaded, or can be manually cleared before a
reload by writing a logic 1 to CLDOK. This bit cannot be written with a zero. LDOK can be set in
DMA mode when the DMA indicates that it has completed the update of all PRSC, INIT, VALx,
fields. Reset clears LDOK.
0 Do not load new values.
1 Load prescaler, modulus, and PWM values.
For proper initialization of the LDOK and RUN bits, see Section 25.9.5, “Initialization.
Figure 358. Fault Control Register (FCTRL)
Address: Base + 0x014C Access: User read/write
0123456789101112131415
R
FLVL FAUTO FSAFE FIE
W
Reset0000000000000000