Reset Generation Module (MC_RGM) RM0046
204/936 Doc ID 16912 Rev 5
PHASE0 Phase
This phase is entered immediately from any phase on a power-on or enabled ‘destructive’
reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of
the following:
● all enabled ‘destructive’ resets have been processed
● all processes that need to be done in PHASE0 are completed
– 16 MHz IRC stable, VREG voltage okay
● a minimum of 3 16 MHz internal RC oscillator clock cycles have elapsed since power-
up completion and the last enabled ‘destructive’ reset event
PHASE1 Phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3,
or IDLE on a non-masked external or ‘functional’ reset event if it has not been configured to
trigger a ‘short’ sequence. The reset state machine exits PHASE1 and enters PHASE2 on
verification of the following:
● all enabled, non-shortened ‘functional’ resets have been processed
● a minimum of 350 16 MHz internal RC oscillator clock cycles have elapsed since the
last enabled external or non-shortened ‘functional’ reset event
PHASE2 Phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and
enters PHASE3 on verification of the following:
● all processes that need to be done in PHASE2 are completed
– code and data flash initialization
● a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since entering
PHASE2
PHASE3 Phase
This phase is a entered either on exit from PHASE2 or immediately from IDLE on an
enabled, shortened ‘functional’ reset event. The reset state machine exits PHASE3 and
enters IDLE on verification of the following:
● all processes that need to be done in PHASE3 are completed
– code and data flash initialization
● a minimum of 40 16 MHz internal RC oscillator clock cycles have elapsed since the last
enabled, shortened ‘functional’ reset event
IDLE Phase
This is the final phase and is entered on exit from PHASE3. When this phase is reached, the
MC_RGM releases control of the system to the platform and waits for new reset events that
can trigger a reset sequence.
8.4.2 Destructive Resets
A ‘destructive’ reset indicates that an event has occurred after which critical register or
memory content can no longer be guaranteed.
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