FlexPWM RM0046
694/936 Doc ID 16912 Rev 5
Figure 380. Output voltage waveforms
25.8.11 Output logic
Figure 381 shows the output logic of each submodule including how each PWM output has
individual fault disabling, polarity control, and output enable. This allows for maximum
flexibility when interfacing to the external circuitry.
The PWMA and PWMB signals that are output from the deadtime logic in Figure 381 are
positive true signals. In other words, a high level on these signals should result in the
corresponding transistor in the PWM inverter being turned ON. The voltage level required at
the PWM output pin to turn the transistor ON or OFF is a function of the logic between the
pin and the transistor. Therefore, it is imperative that the user program the POLA and POLB
bits before enabling the output pins. A fault condition can result in the PWM output being
tristated, forced to a logic 1, or forced to a logic 0 depending on the values programmed into
the PWMxFS fields.
Deadtime
PWM to top
Positive
Negative
PWM to bottom
Load voltage with
Load voltage with
transistor
transistor
high positive current
low positive current
current
current
Load voltage with
high negative current
Load voltage with
low negative current
TBTB
T = Deadtime interval before assertion of top PWM
B = Deadtime interval before assertion of bottom PWM
V+
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