RM0046 Cross Triggering Unit (CTU)
Doc ID 16912 Rev 5 617/936
24.8 Memory map
ORed onto
FIFO2_I (IRQ203)
FIFO_FULL1 This bit is set to 1 if the FIFO 1 is full.
FIFO_EMPTY1 This bit is set to 1 if the FIFO 1 is empty.
FIFO_OVERFLOW
1
This bit is set to 1 if the number of words exceeds the value set in the
threshold 1.
FIFO_OVERRUN1
This bit is set to 1 if a write operation occurs when corresponding
FIFO_FULL1 flag is set.
ORed onto
FIFO3_I (IRQ204)
FIFO_FULL2 This bit is set to 1 if the FIFO 2 is full.
FIFO_EMPTY2 This bit is set to 1 if the FIFO 2 is empty.
FIFO_OVERFLOW
2
This bit is set to 1 if the number of words exceeds the value set in the
threshold 2.
FIFO_OVERRUN2
This bit is set to 1 if a write operation occurs when corresponding
FIFO_FULL2 flag is set.
ORed onto
FIFO4_I (IRQ205)
FIFO_FULL3 This bit is set to 1 if the FIFO 3 is full.
FIFO_EMPTY3 This bit is set to 1 if the FIFO 3 is empty.
FIFO_OVERFLOW
3
This bit is set to 1 if the number of words exceeds the value set in the
threshold 3.
FIFO_OVERRUN3
This bit is set to 1 if a write operation occurs when corresponding
FIFO_FULL3 flag is set.
ORed onto ERR_I
(IRQ207)
MRS_RE Master Reload Signal Reload Error
SM_TO Trigger Overrun (more than 8 EV) in TGS Sequential Mode
ICE Invalid Command Error
MRS_O Master Reload Signal Overrun
TGS_OSM TGS Overrun in Sequential Mode
ADC_OE ADC command generation Overrun Error
T0_OE Timer 0 trigger generation Overrun Error
T1_OE Timer 1 trigger generation Overrun Error
ET_OE External Trigger generation Overrun Error
Table 311. CTU interrupts (continued)
Category Interrupt Interrupt function
Table 312. CTU memory map
Offset from
CTU_BASE
(0xFFE0_C000)
Register Location
0x0000
TGSISR — Trigger Generator Subunit Input Selection
Register
on page 24-621
0x0004 TGSCRR — Trigger Generator Subunit Control Register on page 24-624
0x0006 T0CR — Trigger 0 Compare Register on page 24-624
To Next Page
Loading...
