Mode Entry Module (MC_ME) RM0046
180/936 Doc ID 16912 Rev 5
6.4.4 Protection of Mode Configuration Registers
While programming the mode configuration registers ME_<mode>_MC, the following rules
must be respected. Otherwise, the write operation is ignored and an invalid mode
configuration interrupt may be generated.
● If the 16 MHz int. RC osc. is selected as the system clock, 16 MHz_IRC must be on.
● If the 4 MHz crystal osc. clock is selected as the system clock, OSC must be on.
● If the system PLL clock is selected as the system clock, PLL must be on.
● The 4 MHz crystal oscillator must be on if the system PLL is on. Therefore, when
writing a ‘1’ to PLL0ON, a ‘1’ must also be written to XOSC0ON.
Note: Software must ensure that clock sources with dependencies other than those mentioned
above are swithced on as needed. There is no automatic protection mechanism to check
this in the MC_ME.
● Configuration “00” for the CFLAON and DFLAON bit fields is reserved.
● Configuration “10” for the DFLAON bit field is reserved.
● If the DFLAON bit field is set to “11”, the CFLAON field must also be set to “11”.
● System clock configurations marked as ‘reserved’ may not be selected.
● Configuration “1111” for the SYSCLK bit field is allowed only for theTEST mode, and
only in this case may all system clock sources be turned off.
Warning: If the system clock is stopped during TEST mode, the device
can exit only via a system reset.
6.4.5 Mode Transition Interrupts
The MC_ME provides interrupts for incorrectly configuring a mode, requesting an invalid
mode transition, indicating a SAFE mode transition not due to a software request, and
indicating when a mode transition has completed.
Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the
protection rules mentioned in the Section 6.4.4, “Protection of Mode Configuration
Registers, the interrupt pending bit I_ICONF of the ME_IS register is set and an interrupt
request is generated if the mask bit M_ICONF of ME_IM register is ‘1’.
Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions:
● If the system is in the SAFE mode and the SAFE mode request from MC_RGM is
active, and if the target mode requested is other than RESET or SAFE, then this new
mode request is considered to be invalid, and the S_SEA bit of the ME_IMTS register is
set.
● If the TARGET_MODE bit field of the ME_MCTL register is written with a value different
from the specified mode values (i.e., a non-existing mode), an invalid mode transition
event is generated. When such a non existing mode is requested, the S_NMA bit of the
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