ST SPC560P34 - Register Protection; External Signal Description; Detailed Signal Descriptions; Table 89. SIUL Signal Properties

System Integration Unit Lite (SIUL) RM0046
250/936 Doc ID 16912 Rev 5
11.3.1 Register protection
Most of the configuration registers of the System Integration Unit Lite are protected from
accidental writes, see Appendix A: Registers Under Protection.
11.4 External signal description
The pad configuration allows flexible, centralized control of the pin electrical characteristics
of the MCU with the GPIO control providing centralized general purpose I/O for an MCU that
multiplexes GPIO with other signals at the I/O pads. These other signals, or alternate
functions, will normally be the peripherals functions. The internal multiplexing allows user
selection of the input to chip-level signal multiplexers. Each GPIO port communicates via 16
I/O channels. In order to use the pad as a GPIO, the corresponding Pad Configuration
Registers (PCR[0:71]) for all pads used in the port must be configured as GPIO rather than
as the alternate pad function.
Table 8 9 lists the external pins used by the SIUL.
(
11.4.1 Detailed signal descriptions
General-purpose I/O pins (GPIO[0:66])
The GPIO pins provide general-purpose input and output function. The GPIO pins are
generally multiplexed with other I/O pin functions. Each GPIO input and output is separately
controlled by an input (GPDIn_n) or output (GPDOn_n) register.
See Section , “GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) and
Section , “GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]).
External interrupt request input pins (EIRQ[0:24])
The EIRQ[0:24] are connected to the SIUL inputs. Rising or falling edge events are enabled
by setting the corresponding bits in the “n” SIUL_IREER or the SIUL_IFEER register. See
Section , “Interrupt Rising-Edge Event Enable Register (IREER) and Section , “Interrupt
Falling-Edge Event Enable Register (IFEER).
Table 89. SIUL signal properties
GPIO category Name I/O direction Function
System configuration
GPIO[0:19],
GPIO[22],
GPIO[35:62]
Input/Output General-purpose input/output
GPIO[23:34],
GPIO[63],
GPIO[65:66]
Input Analog precise channel pins
External interrupt EIRQ[0:24] Input
Pins with External Interrupt Request functionality.
Please refer to the signal description chapter of this
reference manual for details.