RM0046 Clock Generation Module (MC_CGM)
Doc ID 16912 Rev 5 125/936
5.5.3 System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
Table 27. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions
Field Description
SELDIV
Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL
Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 16 MHz int. RC osc.
0001 4 MHz crystal osc.
0010 system PLL
0011 reserved
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Figure 29. System Clock Select Status Register (CGM_SC_SS)
Address 0xC3FE_0378 Access: User read, Supervisor read, Test read
0123456789101112131415
R0000 SELSTAT 00000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
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