RM0046 Introduction
Doc ID 16912 Rev 5 63/936
● End-of-transmission interrupt flag
● Programmable transfer baud rate
● Programmable data frames from 4 to 16 bits
● Up to 8 chip select lines available:
– 8 on DSPI_0
– 4 each on DSPI_1 and DSPI_2
● 8 clock and transfer attributes registers
● Chip select strobe available as alternate function on one of the chip select pins for
deglitching
● FIFOs for buffering up to 4 transfers on the transmit and receive side
● Queueing operation possible through use of the I/O processor or eDMA
● General purpose I/O functionality on pins when not used for SPI
1.6.24 Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules each of which is
set up to control a single half-bridge power stage. There are also three fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM),
permanent magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors
(BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
The FlexPWM block implements the following features:
● 16-bit resolution for center, edge-aligned, and asymmetrical PWMs
● Clock frequency same as that used for e200z0h core
● PWM outputs can operate as complementary pairs or independent channels
● Can accept signed numbers for PWM generation
● Independent control of both edges of each PWM output
● Synchronization to external hardware or other PWM supported
● Double buffered PWM registers
– Integral reload rates from 1 to 16
– Half cycle reload capability
● Multiple ADC trigger events can be generated per PWM cycle via hardware
● Write protection for critical registers
● Fault inputs can be assigned to control multiple PWM outputs
● Programmable filters for fault inputs
● Independently programmable PWM output polarity
● Independent top and bottom deadtime insertion
● Each complementary pair can operate with its own PWM frequency and deadtime
values
● Individual software-control for each PWM output
● All outputs can be programmed to change simultaneously via a “Force Out” event
● PWMX pin can optionally output a third PWM signal from each submodule
● Channels not used for PWM generation can be used for buffered output compare
functions
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