RM0046 Flash Memory
Doc ID 16912 Rev 5 317/936
Likewise, the bank1 logic includes a single 128-bit temporary holding register and
sequential accesses that “hit” in this register are also serviced with a 0 wait state response.
17.2.10 Write cycles
In a write cycle, address, write data, and control signals are launched off the same edge of
hclk at the completion of the first AHB data phase cycle. Write cycles to the Flash array are
initiated by driving a valid access address on bkn_fl_addr[23:0], driving write data on
bkn_fl_wdata[63:0], and asserting bkn_fl_wr_en. Again, the controller drives the address
and control information for the required setup time before the rising edge of hclk, and
provides the required amount of hold time. The platform Flash controller then waits for the
appropriate number of write wait states before terminating the write operation. On the cycle
following the programmed wait state value, the platform Flash controller asserts hready_out
to indicate to the AHB port that the cycle has terminated.
17.2.11 Error termination
The platform Flash controller follows the standard procedure when an AHB bus cycle is
terminated with an ERROR response. First, the platform Flash controller asserts hresp[0]
and negates hready_out to signal an error has occurred. On the following clock cycle, the
platform Flash controller asserts hready_out and holds both hresp[0] and hready_out
asserted until hready_in is asserted.
The first case that can cause an error response to the AHB is when an access is attempted
by an AHB master whose corresponding Read Access Control or Write Access Control
settings do not allow the access, thus causing a protection violation. In this case, the
platform Flash controller does not initiate a Flash array access.
The second case that can cause an error response to the AHB is when an access is
performed to the Flash array and is terminated with a Flash error response. See
Section 17.2.13, “Flash error response operation. This may occur for either a read or a write
operation.
The third case that can cause an error response to the AHB is when a write access is
attempted to the Flash array and is disallowed by the state of the bkn_fl_ary_access control
input. This case is similar to case 1.
A fourth case involves an attempted read access while the Flash array is busy doing a write
(program) or erase operation if the appropriate read-while-write control field is programmed
for this response. The 3-bit read-while-write control allows for immediate termination of an
attempted read, or various stall-while-write/erase operations are occurring.
The platform Flash controller can also terminate the current AHB access if hready_in is
asserted before the end of the current bus access. While this circumstance should not
occur, this does not result in an error condition being reported, as this behavior is initiated by
the AHB. In this circumstance, the platform Flash controller control state machine completes
any Flash array access in progress (without signaling the AHB) before handling a new
access request.
17.2.12 Access pipelining
The platform Flash controller does not support access pipelining since this capability is not
supported by the Flash array. As a result, the APC (Address Pipelining Control) field should
typically be the same value as the RWSC (Read Wait State Control) field for best
performance, that is, BKn_APC = BKn_RWSC. It cannot be less than the RWSC.
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