Nexus Development Interface (NDI) RM0046
868/936 Doc ID 16912 Rev 5
36.10.12 Unconditional Debug Event
An Unconditional debug event (UDE) occurs when the Unconditional Debug Event (p_ude)
input transitions to the asserted state, and either DBCR0
IDM
=1 or DBCR0
EDM
=1. The
Unconditional debug event is the only debug event which does not have a corresponding
enable bit for the event in DBCR0. This event can occur and be recorded in DBSR
regardless of the setting of MSR
DE
. When an Unconditional debug event occurs, the
DBSR
UDE
bit is set to ‘1’ to record the debug exception.
36.11 Debug Registers
This section describes debug-related registers that are software accessible. These registers
are intended for use by special debug tools and debug software, not by general application
code.
Access to these registers by software is conditioned by the External Debug Mode control bit
(DBCR0
EDM
) and the settings of debug control register DBERC0, which can be set by the
hardware debug port. If DBCR0
EDM
is set and if the bit in DBERC0 corresponding to the
resource is cleared, software is prevented from modifying debug register values, since the
resource is not “owned” by software. Execution of a
mtspr instruction targeting a debug
register or register field not “owned” by software will not cause modifications to occur. In
addition, since the external debugger hardware may be manipulating debug register values,
the state of these registers or register fields not “owned” by software is not guaranteed to be
consistent if accessed (read) by software with a
mfspr instruction, other than the
DBCR0
EDM
bit and the DBERC0 register itself. Hardware always has full access to all
registers and all register fields through the OnCE register access mechanism, and it is up to
the debug firmware to properly implement modifications to these registers with read-modify-
write operations to implement any control sharing with software. Settings in DBERC0 should
be considered by the debug firmware in order to preserve software settings of control and
status registers as appropriate when hardware modifications to the debug registers is
performed.
36.11.1 Debug Address and Value Registers
Instruction Address Compare registers IAC1, IAC2, IAC3, and IAC4 are used to hold
instruction addresses for address comparison purposes. In addition, IAC2 and IAC4 hold
mask information for IAC1 and IAC3 respectively when Address Bit Match compare modes
are selected. Note that when performing instruction address compares, the low order bit of
the instruction address and the corresponding IAC register is ignored.
Data Address Compare registers DAC1 and DAC2 are used to hold data access addresses
for address comparison purposes. In addition, DAC2 holds mask information for DAC1 when
Address Bit Match compare mode is selected.
Data Value Compare registers DVC1 and DVC2 are used to hold data values for data
comparison purposes. DVC1 and DVC2 are 32-bit registers. Data value comparisons are
used to qualify Data Address compare debug events. DVC1 is associated with DAC1, and
DVC2 is associated with DAC2. The most significant byte of the DVC1(2) register (labeled
B0 in Figure 506) corresponds to the byte data value transferred to/from memory byte offset
0, and the least significant byte of the register (labeled B3 in Figure 506) corresponds to
byte offset 3. When enabled for performing data value comparisons, each enabled byte in
DVC1(2) is compared with the memory value transferred on the corresponding active
byte
lane of the data memory interface to determine if a match occurs. Inactive byte lanes do not
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