RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 893/936
has been entered, the jd_de_en output will be asserted for three j_tclk periods to signal an
acknowledge. jd_de_en can be used to enable the open-drain pulldown of the system level
DE_b pin.
For systems which do not implement a system level bidirectional open drain debug event pin
DE_b, the jd_de_en and jd_de_b signals may still be used to handshake debug entry.
e200z0h OnCE Debug Output (jd_debug_b)
The e200z0h OnCE Debug output jd_debug_b is used to indicate to on-chip resources that
a debug session is in progress. Peripherals and other units may use this signal to modify
normal operation for the duration of a debug session, which may involve the CPU executing
a sequence of instructions solely for the purpose of visibility/system control which are not
part of the normal instruction stream the CPU would have executed had it not been placed
in debug mode. This signal is asserted the first time the CPU enters the debug state, and
remains asserted until the CPU is released by a write to the e200z0h OnCE Command
Register with the GO and EX bits set, and a register specified as either “No Register
Selected” or the CPUSCR. This signal will remain asserted even though the CPU may enter
and exit the debug state for each instruction executed under control of the e200z0h OnCE
controller. See Section for more information on the function of the GO and EX bits. This
signal is not normally used by the CPU.
e200z0h CPU Clock On Input (jd_mclk_on)
The e200z0h CPU Clock On input jd_mclk_on is used to indicate that the CPU’s m_clk
input is active. This input signal is expected to be driven by system logic external to the
e200z0h core, is synchronized to the j_tclk (scan clock) clock domain, and is presented as
a status flag on the j_tdo output during the Shift_IR state. External firmware may use this
signal to ensure proper scan sequences will occur to access debug resources in the m_clk
clock domain.
Watchpoint Events (jd_watchpt[0:5])
The jd_watchpt[0:5] signals may be asserted by the e200z0h OnCE control logic to signal
that a watchpoint condition has occurred. Watchpoints do not cause the CPU to be affected.
They are provided to allow external visibility only. Watchpoint events are conditioned by the
settings in the DBCRx registers.
36.12.5 e200z0h OnCE Controller and Serial Interface
The OnCE Controller contains the OnCE command register, the OnCE decoder, and the
status/control register. Figure 515 is a block diagram of the OnCE controller. In operation,
the OnCE Command register acts as the IR for the e200z0h TAP controller, and all other
OnCE resources are treated as data registers (DR) by the TAP controller. The Command
register is loaded by serially shifting in commands during the TAP controller Shift-IR state,
and is loaded during the Update-IR state. The Command register selects a resource to be
accessed as a data register (DR) during the TAP controller Capture-DR, Shift-DR and
Update-DR states.
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