RM0046 System Integration Unit Lite (SIUL)
Doc ID 16912 Rev 5 269/936
active falling edge or both edges being active. A setting of having both edge events disabled
is reserved and should not be configured.
The active EIRQ edge is controlled through the configuration of the registers IREER and
IFEER.
Each external interrupt supports an individual flag that is held in the ISR (see Section ,
“Interrupt Status Flag Register (ISR)). This register is a write-1-to-clear register type,
preventing inadvertent overwriting of other flags in the same register.
11.7 Pin muxing
For pin muxing, please refer to Chapter 3: Signal Description of this reference manual.
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