Introduction RM0046
52/936 Doc ID 16912 Rev 5
1.4 Critical performance parameters
● Fully static operation, 0–64 MHz
● –40 °C to 150 °C junction temperature
â—Ź Low power design
– Less than 450 mW power dissipation
– Halt and STOP mode available for power reduction
– Resuming from Halt/STOP mode can be initiated via external pin
â—Ź Fabricated in 90 nm process
â—Ź 1.2 V nominal internal logic
â—Ź Nexus pins operate at V
DDIO
(no dedicated power supply)
– Unused pins configurable as GPIO
● 10-bit ADC conversion time < 1 µs
â—Ź Internal voltage regulator (VREG) with external ballast transistor enables control with a
single input rail
– 3.0 V–3.6 V or 4.5 V–5.5 V input supply voltage
â—Ź Configurable pins
– Selectable slew rate for EMI reduction
– Selectable pull-up, pull-down, or no pull on all pins
– Selectable open drain
– Support for 3.3 V or 5 V I/O levels
1.5 Chip-level features
On-chip modules available within the family include the following features:
â—Ź Single issue, 32-bit CPU core complex (e200z0h)
– Compliant with Power Architecture™ embedded category
– Variable Length Encoding (VLE)
â—Ź Memory
– Up to 256 KB on-chip Code Flash with ECC and erase/program controller
– Up to additional 64 (4 × 16) KB on-chip Data Flash with ECC for EEPROM
emulation
– Up to 20 KB on-chip SRAM with ECC
â—Ź Fail-safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
â—Ź Nexus L1 interface
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