Error Correction Status Module (ECSM) RM0046
306/936 Doc ID 16912 Rev 5
15.4.3 ECSM_reg_protection
The ECSM_reg_protection logic provides hardware enforcement of supervisor mode access
protection for four on-platform IPS modules: INTC, ECSM, STM, and SWT. This logic
resides between the on-platform bus sourced by the PBRIDGE bus controller and the
individual slave modules. It monitors the bus access type (supervisor or user) and if a user
access is attempted, the transfer is terminated with an error and inhibited from reaching the
slave module. Identical logic is replicated for each of the five, targeted slave modules. A
block diagram of the ECSM_reg_protection module is shown in Figure 143.
Figure 142. Platform RAM ECC Data register (PREDR)
Address:
Base + 0x006C Access: User read-only
0123456789101112131415
R REDR[31:16]
W
Reset————————————————
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REDR[15:0]
W
Reset————————————————
Table 133. REDR field descriptions
Name Description
0-31
REDR[31:0]
RAM ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last properly
enabled RAM ECC event. The register contains the data value taken directly from the data bus.
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