RM0046 LIN Controller (LINFlex)
Doc ID 16912 Rev 5 493/936
Table 234. LINCR1 field descriptions
Field Description
CCD
Checksum calculation disable
This bit disables the checksum calculation (see Tabl e 2 35).
0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only.
1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can
program this register to send a software-calculated CRC (provided CFD is 0).
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
CFD
Checksum field disable
This bit disables the checksum field transmission (see Tabl e 2 35).
0 Checksum field is sent after the required number of data bytes is sent.
1 No checksum field is sent.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
LASE
LIN Slave Automatic Resynchronization Enable
0 Automatic resynchronization disable.
1 Automatic resynchronization enable.
This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
AWUM
Automatic Wake-Up Mode
This bit controls the behavior of the LINFlex hardware during Sleep mode.
0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR.
1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection. The
SLEEP bit of the LINCR is cleared by hardware whenever WUF bit in the LINSR is set.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
MBL
LIN Master Break Length
This field indicates the Break length in Master mode (see Table 2 36).
Note: This field can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
BF
Bypass filter
0 No interrupt if identifier does not match any filter.
1 An RX interrupt is generated on identifier not matching any filter.
– If no filter is activated, this bit is reserved.
– This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SFTM
Self Test Mode
This bit controls the Self Test mode. For more details, see Section 21.6.2, Self Test mode.
0 Self Test mode disable.
1 Self Test mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
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