RM0046 LIN Controller (LINFlex)
Doc ID 16912 Rev 5 501/936
UART mode control register (UARTCR)
CEF
Checksum Error Flag
This bit is set by hardware and indicates that the received checksum does not match the hardware
calculated checksum.
This bit is cleared by software.
Note: This bit is never set if CCD or CFD bit in LINCR1 is set.
SFEF
Synch Field Error Flag
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch
Field).
BDEF
Break Delimiter Error Flag
This bit is set by hardware and indicates that the received Break Delimiter is too short (less than
one bit time).
IDPEF
Identifier Parity Error Flag
This bit is set by hardware and indicates that a Identifier Parity error occurred.
Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in
LINIER is set.
FEF
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a framing error
(invalid stop bit). This error can occur during reception of any data in the response field (Master or
Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
BOF
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If
RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte
overwrites the buffer. It can be cleared by software.
NF
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
Table 240. LINESR field descriptions (continued)
Field Description
Figure 239. UART mode control register (UARTCR)
Offset: 0x0010 Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
TDFL
0
RDFL
0000
RXEN
TXEN
OP PCE WL
UART
W
Reset0000000000000000
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