ST SPC560P34 - Debug External Resource Control Register (DBERC0)

Nexus Development Interface (NDI) RM0046
882/936 Doc ID 16912 Rev 5
36.11.3 Debug External Resource Control Register (DBERC0)
The Debug External Resource Control Register (DBERC0) controls resource allocation
when DBCR0
EDM
is set to ‘1’. DBERC0 provides a mechanism for the hardware debugger
to share certain debug resources with software. Individual resources are allocated based on
the settings of DBERC0 when DBCR0
EDM
=1. DBERC0 settings are ignored when
DBCR0
EDM
=0.
Hardware-owned resources which generate debug events update DBSR and cause entry
into debug mode, while software-owned resources which generate debug events if
DBCR0
IDM
=1, update DBSR and act as if they occurred in internal debug mode, thus
causing debug interrupts to occur if MSR
DE
=1. DBERC0 is controlled via the OnCE port
hardware, and is read-only to software.
Debug status bits in DBSR are set by software-owned debug events only while Internal
Debug Mode is enabled. When debug interrupts are enabled (MSR
DE
=1 DBCR0
IDM
=1 and
DBCR0
EDM
=0, or MSR
DE
=1, DBCR0
IDM
=1 and DBCR0
EDM
=1 and software is allocated
15 DAC2W
Data Address Compare 2 Write Debug Event
Set to ‘1’ if a write-type DAC2 debug event occurred while DBCR0
DAC2
=0b01 or
DBCR0
DAC2
=0b11
16 RET
Return Debug Event
Set to ‘1’ if a Return debug event occurred
17:20 — Reserved
21 DEVT1
External Debug Event 1 Debug Event
Set to ‘1’ if a DEVT1 debug event occurred
22 DEVT2
External Debug Event 2 Debug Event
Set to ‘1’ if a DEVT2 debug event occurred
23:24 — Reserved
25 CIRPT
Critical Interrupt Taken Debug Event
Set to ‘1’ if a Critical Interrupt Taken debug event occurred.
26 CRET
Critical Return Debug Event
Set to ‘1’ if a Critical Return debug event occurred
27 VLES
VLE Status
Set to ‘1’ if an ICMP, BRT, TRAP, RET, CRET, IAC, or DAC debug event occurred on a
Power Architecture technology VLE Instruction. Undefined for IRPT, CIRPT, DEVT[1,2],
and UDE events
28 — Reserved
29:30 DAC_OFST
Data Address Compare Offset
Indicates offset-1 of saved DSRR0 value from the address of the load or store instruction
which took a DAC Debug exception, unless a simultaneous DSI error occurs, in which
case this field is set to 2‘b00 and DBSR
IDE
is set to ‘1’. Normally set to 2‘b00 by a non-
DVC DAC. A DVC DAC may set this field to any value.
31 — Reserved
Table 463. DBSR Bit Definitions (continued)
Bit(s) Name Description