ST SPC560P34 - Voltage Regulators and Power Supplies

Voltage Regulators and Power Supplies RM0046
836/936 Doc ID 16912 Rev 5
34 Voltage Regulators and Power Supplies
34.1 Voltage regulator
The power blocks are used for providing 1.2 V digital supply to the internal logic of the
device. The main/input supply is 3.3 V to 5.0 V ±10% and the digital/regulated output supply
has a trim target voltage of 1.28 V. The voltage regulator used in SPC560P40/34 is the high
power or main regulator (HPREG).
The internal voltage regulator requires an external ballast transistor and (external)
capacitance (CREG) to be connected to the device in order to provide a stable low voltage
digital supply to the device. Capacitances should be placed on the board as near as
possible from the associated pins.The regulator has a digital domain called the High Power
domain that has a low voltage detector for the 1.2 V output voltage. Additionally, there are
two low voltage detectors for the main/input supply with different threshold, one at 3.3 V
level and the other one at 5 V level.
34.1.1 High Power or Main Regulator (HPREG)
The HPREG converts the 3.3 V–5 V input supply to a 1.2 V digital supply. The nominal
target output is 1.28 V. Due to all variations, the actual output will be in range of 1.08 V to
1.32 V in the full current load range (0–250 mA) after trimming.
The stabilization for HPREG is achieved using an external capacitance. The minimum
recommended value is 3 × 10 µF with low ESR (refer to datasheet for details).
Note: In general an offset voltage must be avoided to pre-charge V
DD_HV_REG
through parasitic
paths to allow a correct power up sequence.
The MCU supply must power on from GND to power supply with a monotonic ramp,
minimum and maximum values as described in the data sheet (TV
DD
).
34.1.2 Low Voltage Detectors (LVD) and Power On Reset (POR)
Five types of low voltage detectors are provided on the device:
● V
REGLVDMOK_L
monitors the 3.3 V regulator supply
● V
FLLVDMOK_L
monitors the 3.3 V flash supply
● V
IOLVDMOK_L
monitors the 3.3 V I/O supply
● V
IOLVDM5OK_L
monitors the 5 V I/O supply
● V
MLVDDOK_L
monitors the 1.2 V digital logic supply
LVD_MAIN is the main voltage LVD with a threshold set around 2.7 V. LVD_MAIN5 is the
main voltage LVD with a threshold set around 4 V. The LVD_MAIN and LVD_MAIN5 sense
the 3.3 V–5 V power supply for CORE, shared with IO ring supply and indicate when the
3.3 V–5 V supply is stabilized. The threshold levels of LVD_MAIN5 are trimmable with the
help of LVDM5[0:3] trim bits.
The LVD_MAIN and LVD_MAIN5 detectors sense the V
DDIO
supply and provide
V
IOLVDMOK_H
/V
IOLVDM5OK_H
and V
IOLVDMOK_L
/V
IOLVDM5OK_L
as active high signals at 3.3 V
and 1.2 V supply levels, respectively.
Two more LVD_MAIN detectors are also used for sensing VDDREG and VDDFLASH.