FlexCAN RM0046
550/936 Doc ID 16912 Rev 5
Rx Global Mask register (RXGMASK)
This register is provided for legacy support and for low cost MCUs that do not have the
individual masking per Message Buffer feature. For MCUs supporting individual masks per
MB, setting the BCC bit in the MCR causes the RXGMASK register to have no effect on the
module operation. For MCUs not supporting individual masks per MB, this register is always
effective.
RXGMASK is used as an acceptance mask for all Rx MBs, excluding MBs 14
–15, which
have individual mask registers. When the FEN bit in the MCR is set (FIFO enabled), the
RXGMASK also applies to all elements of the ID filter table, except elements 6–7, which
have individual masks.
The contents of this register must be programmed while the module is in Freeze Mode, and
must not be modified when the module is transmitting or receiving frames.
Figure 267. Free Running Timer (TIMER)
Address:
Base + 0x0008 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TIMER
W
Reset0000000000000000
Table 276. TIMER field descriptions
Field Description
TIMER Holds the value for this timer.
Figure 268. Rx Global Mask register (RXGMASK)
Address:
Base + 0x0010 Access: User read/write
0123456789101112131415
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset1111111111111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset1111111111111111
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