ST SPC560P34 - Instruction Address Compare Event

Nexus Development Interface (NDI) RM0046
862/936 Doc ID 16912 Rev 5
cause debug exceptions and set DBSR bits regardless of the state of MSR
DE
. A Debug
interrupt will be delayed until MSR
DE
is later set to ‘1’.
When a Debug Status Register bit is set while MSR
DE
=0, and DBCR0
EDM
=0 or
DBCR0
EDM
=1 and the corresponding resource is owned (via DBERC0) by software debug,
an Imprecise Debug Event flag (DBSR
IDE
) will also be set to indicate that an exception bit in
the Debug Status Register was set while Debug interrupts were disabled. Debug interrupt
handler software can use this bit to determine whether the address recorded in
Debug Save/Restore Register 0 is an address associated with the instruction causing the
debug exception, or the address of the instruction which enabled a delayed Debug interrupt
by setting the MSR
DE
bit. A mtmsr or mtdbcr0 which causes both MSR
DE
and DBCR0
IDM
to become set, enabling precise debug mode, may cause an Imprecise (Delayed) Debug
exception to be generated due to an earlier recorded event in the Debug Status register.
There are eight types of debug events defined by Power Architecture technology:
2. Instruction Address Compare debug events
3. Data Address Compare debug events
4. Trap debug events
5. Branch Taken debug events
6. Instruction Complete debug events
7. Interrupt Taken debug events
8. Return debug events
9. Unconditional debug events
In addition, e200z0h defines additional debug events:
● The External debug events DEVT1 and DEVT2 which are described in
Section 36.10.11, “External Debug Event.
● The Critical Interrupt Taken debug event CIRPT which is described in Section 36.10.8,
“Critical Interrupt Taken Debug Event.
● The Critical Return debug event CRET which is described in Section 36.10.10, “Critical
Return Debug Event.
The e200z0h debug configuration supports most of these event types. Unsupported Power
Architecture technology functionality is as follows:
● Instruction Address Compare and Data Address Compare Real address mode is not
supported
A brief description of each of the event types follows. In these descriptions, DSRR0 and
DSRR1 are used, assuming that the Debug APU is enabled. If it is disabled, use CSRR0
and CSRR1 respectively.
36.10.1 Instruction Address Compare Event
Instruction Address Compare debug events occur when enabled and execution is attempted
of an instruction at an address that meets the criteria specified in the DBCR0, DBCR1,
IAC1, IAC2, IAC3, and IAC4 Registers. Instruction Address compares may specify
user/supervisor mode and instruction space (MSR
IS
), along with an effective address,
masked effective address, or range of effective addresses for comparison. This event can
occur and be recorded in DBSR regardless of the setting of MSR
DE
. IAC events will not
occur when an instruction would not have normally begun execution due to a higher priority
exception at an instruction boundary.