ST SPC560P34 - Table 281. Fault Confinement State; Figure 273. Interrupt Masks 1 Register (IMASK1)

FlexCAN RM0046
556/936 Doc ID 16912 Rev 5
Interrupt Masks 1 Register (IMASK1)
This register allows to enable or disable any number of a range of 32 Message Buffer
Interrupts. It contains one interrupt mask bit per buffer, enabling the CPU to determine which
buffer generates an interrupt after a successful transmission or reception (that is, when the
corresponding IFLAG1 bit is set).
29
BOFF_INT
Bus Off Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control
Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it
to 1. Writing 0 has no effect.
0 No such occurrence.
1 FlexCAN module entered ‘Bus Off’ state.
30
ERR_INT
Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16–21) is set. If the corresponding mask bit
in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to 1.Writing 0 has no effect.
0 No such occurrence.
1 Indicates setting of any Error Bit in the Error and Status Register.
31
Wake-Up Interrupt
When FlexCAN is in Stop Mode and a recessive to dominant transition is detected on the CAN bus
and if the WAK_MSK bit in the MCR is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to 1. Writing 0 has no effect.
0 No such occurrence.
1 Indicates a recessive to dominant transition received on the CAN bus when the FlexCAN module
is in Stop Mode.
Table 280. Error and Status Register (ESR) field description (continued)
Field Description
Table 281. Fault confinement state
Value Meaning
00 Error Active
01 Error Passive
1X Bus Off
Figure 273. Interrupt Masks 1 Register (IMASK1)
Address: Base + 0x0028 Access: User read/write
0123456789101112131415
R
BUF
31M
BUF
30M
BUF
29M
BUF
28M
BUF
27M
BUF
26M
BUF
25M
BUF
24M
BUF
23M
BUF
22M
BUF
21M
BUF
20M
BUF
19M
BUF
18M
BUF
17M
BUF
16M
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
15M
BUF
14M
BUF
13M
BUF
12M
BUF
11M
BUF
10M
BUF
9M
BUF
8M
BUF
7M
BUF
6M
BUF
5M
BUF
4M
BUF
3M
BUF
2M
BUF
1M
BUF
0M
W
Reset0000000000000000