ST SPC560P34 - Page 555

RM0046 FlexCAN
Doc ID 16912 Rev 5 555/936
18
ACK_ERR
Acknowledge Error
This bit indicates that an Acknowledge Error has been detected by the transmitter node, that is, a
dominant bit has not been detected during the ACK SLOT.
0 No such occurrence.
1 An ACK error occurred since last read of this register
19
CRC_ERR
Cyclic Redundancy Check Error
This bit indicates that a CRC Error has been detected by the receiver node, that is, the calculated
CRC is different from the received.
0 No such occurrence.
1 A CRC error occurred since last read of this register.
20
FRM_ERR
Form Error
This bit indicates that a Form Error has been detected by the receiver node, that is, a fixed-form bit
field contains at least one illegal bit.
0 No such occurrence.
1 A Form Error occurred since last read of this register.
21
STF_ERR
Stuffing Error
This bit indicates that a Stuffing Error has been detected.
0 No such occurrence.
1 A Stuffing Error occurred since last read of this register.
22
TX_WRN
TX Error Counter
This bit indicates when repetitive errors are occurring during message transmission.
0 No such occurrence.
1 TX_Err_Counter  96.
23
RX_WRN
Rx Error Counter
This bit indicates when repetitive errors are occurring during message reception.
0 No such occurrence.
1 Rx_Err_Counter 96.
24
IDLE
CAN bus IDLE state
This bit indicates when the CAN bus is in IDLE state.
0 No such occurrence.
1 CAN bus is now IDLE.
25
TXRX
Current FlexCAN status (transmitting/receiving)
This bit indicates if FlexCAN is transmitting or receiving a message when the CAN bus is not in
IDLE state. This bit has no meaning when IDLE is asserted.
0 FlexCAN is receiving a message (IDLE = 0).
1 FlexCAN is transmitting a message (IDLE = 0).
26–27
FLT_CONF
Fault Confinement State
This 2-bit field indicates the Confinement State of the FlexCAN module, as shown in Ta ble 2 81. If
the LOM bit in the Control Register is asserted, the FLT_CONF field will indicate “Error Passive”.
Since the Control Register is not affected by soft reset, the FLT_CONF field will not be affected by
soft reset if the LOM bit is asserted.
Table 280. Error and Status Register (ESR) field description (continued)
Field Description