RM0046 FlexPWM
Doc ID 16912 Rev 5 655/936
5
FULL
Full Cycle Reload
This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule
counter matches the VAL1 register. Either the HALF or FULL bit must be set in order to move the
buffered data into the registers used by the PWM generators. If both the HALF and FULL bits are
set, then reloads can occur twice per cycle.
0 Full-cycle reloads disabled.
1 Full-cycle reloads enabled.
6:7
DT
Deadtime
These read only bits reflect the sampled values of the PWMX input at the end of each deadtime.
Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. Reset
clears these bits.
9:11
PRSC
Prescaler
These buffered read/write bits select the divide ratio of the PWM clock frequency selected by
CLK_SEL as illustrated in Ta bl e 346
15
DBLEN
Double Switching Enable
This read/write bit enables the double switching PWM behavior.
0 Double switching disabled.
1 Double switching enabled.
Table 344. CTRL1 field descriptions (continued)
Field Description
Table 345. PWM reload frequency
LDFQ PWM reload frequency
0000 Every PWM opportunity
0001 Every 2 PWM opportunities
0010 Every 3 PWM opportunities
0011 Every 4 PWM opportunities
0100 Every 5 PWM opportunities
0101 Every 6 PWM opportunities
0110 Every 7 PWM opportunities
0111 Every 8 PWM opportunities
1000 Every 9 PWM opportunities
1001 Every 10 PWM opportunities
1010 Every 11 PWM opportunities
1011 Every 12 PWM opportunities
1100 Every 13 PWM opportunities
1101 Every 14 PWM opportunities
1110 Every 15 PWM opportunities
1111 Every 16 PWM opportunities
To Next Page
Loading...
