LIN Controller (LINFlex) RM0046
494/936 Doc ID 16912 Rev 5
LBKM
Loop Back Mode
This bit controls the Loop Back mode. For more details see Section 21.6.1, Loop Back mode.
0 Loop Back mode disable.
1 Loop Back mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode
MME
Master Mode Enable
0 Slave mode enable.
1 Master mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
SBDT
Slave Mode Break Detection Threshold
0 11-bit break.
1 10-bit break.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
RBLM
Receive Buffer Locked Mode
0 Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming
message is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or
Sleep mode.
SLEEP
Sleep Mode Request
This bit is set by software to request LINFlex to enter Sleep mode.
This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1
and the WUF bit in LINSR are set (see Ta bl e 237).
INIT
Initialization Request
The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset,
LINFlex enters Normal mode when clearing the INIT bit (see Table 237).
Table 234. LINCR1 field descriptions (continued)
Field Description
Table 235. Checksum bits configuration
CFD CCD LINCFR Checksum sent
1 1 Read/Write None
1 0 Read-only None
0 1 Read/Write Programmed in LINCFR by bits CF[0:7]
0 0 Read-only Hardware calculated
Table 236. LIN master break length selection
MBL Length
0000 10-bit
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