RM0046 Cross Triggering Unit (CTU)
Doc ID 16912 Rev 5 613/936
in the upper 16 bits indicate the ADC unit (1 bit) and the channel number (4 bits). The result
registers (only for the FIFOs) can be read from two different addresses in the ADC memory
map. The format of the result depends on the address from which it is read. The available
formats are:
● Unsigned right-justified
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit
resolution and bits [15:10] always return zero when read.
● Signed left-justified
Conversion result is signed left-justified data. Bit [15] is reserved for sign and is always
read as zero for this ADC, bits [14:5] are used for 10-bit resolution, and bits [4:0] always
return zero when read.
24.5 Reload mechanism
Some CTU registers are double-buffered, and the reload is controlled by a reload enable bit,
as the TGSISR_RE bit or the DFE bit, but for the most of the double-buffered registers, the
reload is controlled by the MRS occurrence, and it is synchronized with the beginning of the
CTU control period.
If the MRS occurs while the user is updating some double-buffered registers, eg. some
registers of the triggers list, the new triggers list will be a mix of the old triggers list and the
new triggers list, because the user has not ended the update of the triggers list before the
MRS occurrence.
In order to avoid this case, 1 bit enables the reload operation, that is, to inform the CTU that
the user has ended updates to the double-buffered registers, and the reload can be
performed without problems of mixed scenarios. In order to guarantee the coherency, the
reload of all double-buffered registers is enabled by setting GRE (General Reload Enable)
bit in the CTU Control Register. The user must ensure that all intended double-buffered
registers are updated before a new MRS occurrence. If an MRS occurs before a GRE bit is
set (for example, wrong application timing), the update is not performed, the previous values
of all double-buffered registers remain active, the error flag is set (the MRS_RE bit in the
CTU Error Flag Register) and, if enabled, CTU performs an interrupt request.
All the double-buffered registers use the General Reload Enable (GRE) bit to enable the
reload when the MRS occurs. The GRE bit is R/S (Read/Set) and if this bit is 1, the reload
can be performed, while if this bit is 0, the reload is not performed. A correct reload resets
the GRE bit. None of the double-buffered registers can be written while the GRE bit remains
set. The GRE bit can be reset by the occurrence of the next MRS (that is, a correct reload)
or by software setting the CGRE bit.
The CGRE is reset by hardware after that GRE bit is reset. If the user sets the CGRE bit and
at the same time a MRS occurs, CGRE has the priority so GRE is reset and the reload is not
performed. In the same way, the GRE has the priority when compared with the MRS
occurrence, and the CGRE has the priority compared with the GRE (the two bits are in the
same register so they can be set in the same time). MRS has the priority compared with the
re-synchronization bit of the TGSISR.
In order to verify if a reload error occurs, FGRE (Flag GRE bit in the CTU Control Register)
bit is used. When one of the double-buffered registers is written, this flag is set to 1 and it is
reset by a correct reload. When the MRS occurs while FGRE is 1 and GRE is 1, a correct
reload is performed (because all intended registers have been updated before the MRS
occurs). If FGRE is 1 and GRE is 0, a reload is not performed, the error flag (MRS_RE) is
To Next Page
Loading...
