ST SPC560P34 - Figure 401. Control Register 3 (CTRL3)

eTimer RM0046
718/936 Doc ID 16912 Rev 5
Control register 3 (CTRL3)
MSTR
Master Mode
This bit enables the compare function’s output to be broadcast to the other channels in the module.
The compare signal then can be used to reinitialize the other counters and/or force their OFLAG
signal outputs.
0 Disable broadcast of compare events from this channel.
1 Enable broadcast of compare events from this channel.
OUTMODE
Output Mode
These bits determine the mode of operation for the OFLAG output signal.
0000 Software controlled
0001 Clear OFLAG output on successful compare (COMP1 or COMP2)
0010 Set OFLAG output on successful compare (COMP1 or COMP2)
0011 Toggle OFLAG output on successful compare (COMP1 or COMP2)
0100 Toggle OFLAG output using alternating compare registers
0101 Set on compare with COMP1, cleared on secondary source input edge
0110 Set on compare with COMP2, cleared on secondary source input edge
0111 Set on compare, cleared on counter roll-over
1000 Set on successful compare on COMP1, clear on successful compare on COMP2
1001 Asserted while counter is active, cleared when counter is stopped.
1010 Asserted when counting up, cleared when counting down.
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Enable gated clock output while counter is active
Table 374. CTRL2 field descriptions (continued)
Field Description
Figure 401. Control register 3 (CTRL3)
Address:
Base + 0x0012 (eTimer0)
Base + 0x0032 (eTimer1)
Base + 0x0052 (eTimer2)
Base + 0x0072 (eTimer3)
Base + 0x0092 (eTimer4)
Base + 0x00B2 (eTimer5)
Access: User read/write
0123456789101112131415
R
STPEN
ROC
0111
1 C2FCNT[2:0] C1FCNT[2:0]
DBGEN
[1:0]
W
Reset0000111100000000