ST SPC560P34 - Table 275. CTRL Field Descriptions

RM0046 FlexCAN
Doc ID 16912 Rev 5 547/936
Table 275. CTRL field descriptions
Field Description
0–7
PRESDIV
Prescaler Division Factor
This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock)
frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value,
the Sclock frequency is equal to the CPI clock frequency. The Maximum value of this register is
0xFF, that gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For
more information refer to Section , “Protocol timing.
Sclock frequency = CPI clock frequency / (PRESDIV + 1).
8–9
RJW
Resync Jump Width
This 2-bit field defines the maximum number of time quanta
(1)
that a bit time can be changed by
one resynchronization. The valid programmable values are 0–3.
Resync Jump Width = RJW + 1.
10–12
PSEG1
PSEG1 — Phase Segment 1
This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time. The valid
programmable values are 0–7.
Phase Buffer Segment 1(PSEG1 + 1) x Time-Quanta.
13–15
PSEG2
PSEG2 — Phase Segment 2
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid
programmable values are 1–7.
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
16
BOFF_MSK
Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
0 Bus Off interrupt disabled.
1 Bus Off interrupt enabled.
17
ERR_MSK
Error Mask
This bit provides a mask for the Error Interrupt.
0 Error interrupt disabled.
1 Error interrupt enabled.
18
CLK_SRC
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral
clock (driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the
prescaler to generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit
should only be changed while the module is in Disable Mode. See Section , “Protocol timing for
more information.
0 The CAN engine clock source is the oscillator clock.
1 The CAN engine clock source is the bus clock.
Note: This clock selection feature may not be available in all MCUs. A particular MCU may
not have a PLL, in which case it would have only the oscillator clock, or it may use
only the PLL clock feeding the FlexCAN module. In these cases, this bit has no
effect on the module operation.