RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 293/936
ECC registers
There are a number of program-visible registers for the sole purpose of reporting and
logging of memory failures. These registers include the following:
● ECC Configuration Register (ECR)
● ECC Status Register (ESR)
● ECC Error Generation Register (EEGR)
● Flash ECC Address Register (FEAR)
● Flash ECC Master Number Register (FEMR)
● Flash ECC Attributes Register (FEAT)
● Flash ECC Data Register (FEDR)
● RAM ECC Address Register (REAR)
● RAM ECC Syndrome Register (RESR)
● RAM ECC Master Number Register (REMR)
● RAM ECC Attributes Register (REAT)
● RAM ECC Data Register (REDR)
The details on the ECC registers are provided in the subsequent sections. If the design does
not include ECC on the memories, these addresses are reserved locations within the
ECSM’s programming model.
ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of
memory errors are reported. In all systems with ECC, the occurrence of a non-correctable
error causes the current access to be terminated with an error condition. In many cases, this
error termination is reported directly by the initiating bus master. However, there are certain
situations where the occurrence of this type of non-correctable error is not reported by the
master. Examples include speculative instruction fetches, which are discarded due to a
change-of-flow operation, and buffered operand writes. The ECC reporting logic in the
ECSM provides an optional error interrupt mechanism to signal all non-correctable memory
errors. In addition to the interrupt generation, the ECSM captures specific information
(memory address, attributes and data, bus master number, etc.) that may be useful for
subsequent failure analysis.
The reporting of single-bit memory corrections can only be enabled via an SoC-configurable
module input signal. This signal is tied to 1 at SoC level and hence reporting of single-bit
memory corrections is always enabled. While not directly accessible to a user, this capability
is viewed as important for error logging and failure analysis.
Figure 131. ECC Configuration register (ECR)
Address:
Base + 0x0043 Access: User read/write
01234567
R0 0
ER1BR EF1BR
00
ERNCR EFNCR
W
Reset00000000
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