System Timer Module (STM) RM0046
790/936 Doc ID 16912 Rev 5
31 System Timer Module (STM)
31.1 Overview
The System Timer Module (STM) is a 32-bit timer designed to support commonly required
system and application software timing functions. The STM includes a 32-bit up counter and
four 32-bit compare channels with a separate interrupt source for each channel. The counter
is driven by the system clock divided by an 8-bit prescale value (1 to 256).
31.2 Features
The STM has the following features:
● One 32-bit up counter with 8-bit prescaler
● Four 32-bit compare channels
● Independent interrupt source for each channel
● Counter can be stopped in debug mode
31.3 Modes of operation
The STM supports two device modes of operation: normal and debug. When the STM is
enabled in normal mode, its counter runs continuously. In debug mode, operation of the
counter is controlled by the FRZ bit in the STM_CR. If the FRZ bit is set, the counter is
stopped in debug mode, otherwise it continues to run.
31.4 External signal description
The STM does not have any external interface signals.
31.5 Memory map and registers description
The STM programming model has fourteen 32-bit registers. The STM registers can only be
accessed using 32-bit (word) accesses. Attempted references using a different size or to a
reserved address generates a bus error termination. STM registers are accessible only
when the core is in supervisor mode (see Section 15.4.3, “ECSM_reg_protection).
31.5.1 Memory map
The STM memory map is shown in Table 4 2 3.
Table 423. STM memory map
Offset from
STM_BASE
0xFFF3_C000
Register Location
0x0000 STM_CR—STM Control Register on page 31-791
0x0004 STM_CNT—STM Counter Value on page 31-792
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