ST SPC560P34 - Table 460. DBCR1 Bit Definitions

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 873/936
Table 460 provides bit definitions for Debug Control Register 1.
Table 460. DBCR1 Bit Definitions
Bit(s) Name Description
0:1 IAC1US
Instruction Address Compare 1 User/Supervisor Mode
00 – IAC1 debug events not affected by MSR
PR
01 – Reserved
10 – IAC1 debug events can only occur if MSR
PR
=0 (Supervisor mode)
11 – IAC1 debug events can only occur if MSR
PR
=1. (User mode)
2:3 IAC1ER
Instruction Address Compare 1 Effective/Real Mode
00 – IAC1 debug events are based on effective address
01 – Unimplemented in e200z0h (Book E real address compare), no match can occur
10 – IAC1 debug events are based on effective address and can only occur if MSR
IS
=0
11 – IAC1 debug events are based on effective address and can only occur if MSR
IS
=1
4:5 IAC2US
Instruction Address Compare 2 User/Supervisor Mode
00 – IAC2 debug events not affected by MSR
PR
01 – Reserved
10 – IAC2 debug events can only occur if MSR
PR
=0 (Supervisor mode)
11 – IAC2 debug events can only occur if MSR
PR
=1. (User mode)
6:7 IAC2ER
Instruction Address Compare 2 Effective/Real Mode
00 – IAC2 debug events are based on effective address
01 – Unimplemented in e200z0h (Book E real address compare), no match can occur
10 – IAC2 debug events are based on effective address and can only occur if MSR
IS
=0
11 – IAC2 debug events are based on effective address and can only occur if MSR
IS
=1
8:9 IAC12M
Instruction Address Compare 1/2 Mode
00 – Exact address compare. IAC1 debug events can only occur if the address of the instruction
fetch is equal to the value specified in IAC1. IAC2 debug events can only occur if the
address of the instruction fetch is equal to the value specified in IAC2.
01 – Address bit match. IAC1 debug events can occur only if the address of the instruction fetch,
ANDed with the contents of IAC2 are equal to the contents of IAC1, also ANDed with the
contents of IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.
10 – Inclusive address range compare. IAC1 debug events can occur only if the address of the
instruction fetch is greater than or equal to the value specified in IAC1 and less than the
value specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are
used.
11 – Exclusive address range compare. IAC1 debug events can occur only if the address of the
instruction fetch is less than the value specified in IAC1 or is greater than or equal to the
value specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are
used.
10:15 — Reserved
16:17 IAC3US
Instruction Address Compare 3 User/Supervisor Mode
00 – IAC3 debug events not affected by MSR
PR
01 – Reserved
10 – IAC3 debug events can only occur if MSR
PR
=0 (Supervisor mode)
11 – IAC3 debug events can only occur if MSR
PR
=1 (User mode)