Nexus Development Interface (NDI) RM0046
892/936 Doc ID 16912 Rev 5
of the CPU. The CPU core may enter debug mode either through a software or hardware
event.
CPU Address, Attributes
The CPU address and attribute information are used by a Nexus class 2-4 debug unit with
information for real-time address trace information.
CPU Data
The CPU data bus(es) are used to supply a Nexus class 2-4 debug unit with information for
real-time data trace capability.
36.12.4 OnCE Interface Signals
The following paragraphs describe additional OnCE interface signals to other external
blocks such as a Nexus Controller and external blocks which may need information
pertaining to debug operation.
OnCE Enable (jd_en_once)
The OnCE enable signal jd_en_once is used to enable the OnCE controller to allow certain
instructions and operations to be executed. Assertion of this signal will enable the full OnCE
command set, as well as operation of control signals and OnCE Control register functions.
When this signal is disabled, only the Bypass, ID and Enable_OnCE commands are
executed by the OnCE unit, and all other commands default to a “Bypass” command. The
OnCE Status register (OSR) is not visible when OnCE operation is disabled. In addition,
OnCE Control register (OCR) functions are disabled, as is the operation of the jd_de_b
input. Secure systems may choose to leave the jd_en_once signal negated until a security
check has been performed. Other systems should tie this signal asserted to enable full
OnCE operation. The j_en_once_regsel output signal is provided to assist external logic
performing security checks.
The jd_en_once input must only change state during the Test-Logic-Reset, Run-Test/Idle,
or Update_DR TAP states. A new value will take affect after one additional j_tclk cycle of
synchronization. In addition, jd_enable_once input signal must not change state during a
debug session, or undefined activity may occur.
OnCE Debug Request/Event (jd_de_b, jd_de_en)
If implemented at the SoC level, a system level bidirectional open drain debug event pin
DE_b (not part of the interface) provides a fast means of entering the Debug Mode of
operation from an external command controller (when input) as well as a fast means of
acknowledging the entering of the Debug Mode of operation to an external command
controller (when output). The assertion of this pin by a command controller causes the CPU
core to finish the current instruction being executed, save the instruction pipeline
information, enter Debug Mode, and wait for commands to be entered. If DE_b was used to
enter the Debug Mode then DE_b must be negated after the OnCE controller responds with
an acknowledge and before sending the first OnCE command. The assertion of this pin by
the CPU Core acknowledges that it has entered the Debug Mode and is waiting for
commands to be entered.
To support operation of this system pin, the OnCE logic supplies the jd_de_en output and
samples the jd_de_b input when OnCE is enabled (jd_en_once asserted). Assertion of
jd_de_b will cause the OnCE logic to place the CPU into Debug Mode. Once Debug Mode
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