ST SPC560P34 - Table 190. EDMA_HRSL Field Descriptions; Figure 191. EDMA Hardware Request Status Register Low (EDMA_HRSL)

Enhanced Direct Memory Access (eDMA) RM0046
398/936 Doc ID 16912 Rev 5
eDMA Channel n Priority Registers (EDMA_CPRn)
When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the
contents of these registers define the unique priorities associated with each channel within a
group. The channel priorities are evaluated by numeric value; that is, 0 is the lowest priority,
1 is the next higher priority, then 2, 3, etc. If software chooses to modify channel priority
values, then the software must ensure that the channel priorities contain unique values,
otherwise a configuration error is reported. The range of the priority value is limited to the
values of 0 through 15. When read, the GRPPRI bits of the EDMA_CPRn register reflect the
current priority level of the group of channels in which the corresponding channel resides.
GRPPRI bits are not affected by writes to the EDMA_CPRn registers. The group priority is
assigned in the EDMA_CR.
Refer to Figure 177 and Table 1 76 for the EDMA_CR definition.
Channel preemption is enabled on a per-channel basis by setting the ECP bit in the
EDMA_CPRn register. Channel preemption allows the executing channel’s data transfers to
be temporarily suspended in favor of starting a higher priority channel. After the preempting
channel has completed all of its minor loop data transfers, the preempted channel is
restored and resumes execution. After the restored channel completes one read/write
sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel is suspended and the higher priority channel is serviced.
Nested preemption (attempting to preempt a preempting channel) is not supported. After a
preempting channel begins execution, it cannot be preempted. Preemption is only available
when fixed arbitration is selected for both group and channel arbitration modes.
Figure 191. EDMA Hardware Request Status Register Low (EDMA_HRSL)
Address: Base + 0x0034 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HRS
15
HRS
14
HRS
13
HRS
12
HRS
11
HRS
10
HRS
09
HRS
08
HRS
07
HRS
06
HRS
05
HRS
04
HRS
03
HRS
02
HRS
01
HRS
00
W
Reset0000000000000000
Table 190. EDMA_HRSL field descriptions
Field Description
16–31
HRSn
DMA Hardware Request Status
0 A hardware service request for channel n is not present.
1 A hardware service request for channel n is present.
The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore,
this status is affected by the EDMA_ERQRL[ERQn] bit.