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RM0046 FlexCAN

Doc ID 16912 Rev 5 557/936

Interrupt Flags 1 Register (IFLAG1)

This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts. It

contains one interrupt flag bit per buffer. Each successful transmission or reception sets the

corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be

generated. The Interrupt flag must be cleared by writing it to 1. Writing 0 has no effect.

When the AEN bit in the MCR is set (Abort enabled), while the IFLAG1 bit is set for a MB

configured as Tx, the writing access done by CPU into the corresponding MB will be

blocked.

When the FEN bit in the MCR is set (FIFO enabled), the function of the eight least significant

interrupt flags (BUF7I – BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I

and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used.

Table 282. IMASK1 field descriptions

Field Description

0–31

BUF31M –

BUF0M

BUF31M–BUF0M — Buffer MB

Mask

Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) Interrupt.

0 The corresponding buffer Interrupt is disabled.

1The corresponding buffer Interrupt is enabled.

Note: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt

request, if the corresponding IFLAG1 bit is set.

Figure 274. Interrupt Flags 1 Register (IFLAG1)

Address:

Base + 0x0030 Access: User read/write

0123456789101112131415

BUF

31I

BUF

30I

BUF

29I

BUF

28I

BUF

27I

BUF

26I

BUF

25I

BUF

24I

BUF

23I

BUF

22I

BUF

21I

BUF

20I

BUF

19I

BUF

18I

BUF

17I

BUF

16I

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BUF

15I

BUF

14I

BUF

13I

BUF

12I

BUF

11I

BUF

10I

BUF

Reset0000000000000000

Table 283. IFLAG1 field descriptions

Field Description

0–23

BUF31I – BUF8I

Buffer MB

Interrupt

Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.

0 No such occurrence.

1 The corresponding MB has successfully completed transmission or reception.

BUF7I

Buffer MB7 Interrupt or “FIFO Overflow”

If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag

indicates an overflow condition in the FIFO (frame lost because FIFO is full).

0 No such occurrence.

1 MB7 completed transmission/reception or FIFO overflow.

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English

ST SPC560P34 User Manual

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