RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 901/936
36.12.6 Access to Debug Resources
Resources contained in the e200z0h OnCE Module which do not require the e200z0h
processor core to be halted for access may be accessed while the e200z0h core is running,
and will not interfere with processor execution. Accesses to other resources such as the
CPUSCR require the e200z0h core to be placed in debug mode to avoid synchronization
hazards. Debug firmware may ensure that it is safe to access these resources by
determining the state of the e200z0h core prior to access. Note that a scan operation to
update the CPUSCR is required prior to exiting debug mode if debug mode has been
entered.
Some cases of write accesses other than accesses to the OnCE Command and Control
registers, or the EDM bit of DBCR0 require the e200z0h m_clk to be running for proper
operation. The OnCE control register provides a means of signaling this need to a system
level clock control module.
In addition, since the CPU may cause multiple bits of certain registers to change state,
reads of certain registers while the CPU is running (DBSR, etc.) may not have consistent bit
settings unless read twice with the same value indicated. In order to guarantee that the
contents are consistent, the CPU should be placed into debug mode, or multiple reads
should be performed until consistent values have been obtained on consecutive reads.
29 WKUP
Wakeup Request Bit (WKUP)
This control bit may be used to force the e200z0h p_wakeup output signal to be asserted.
This control function may be used by debug firmware to request that the chip-level clock
controller restore the m_clk input to normal operation regardless of whether the CPU is in
a low power state to ensure that debug resources may be properly accessed by external
hardware through scan sequences.
30 FDB
Force Breakpoint Debug Mode Bit (FDB)
This control bit is used to determine whether the processor is operating in breakpoint
debug enable mode or not. The processor may be placed in breakpoint debug enable
mode by setting this bit. In breakpoint debug enable mode, execution of the ‘bkpt’
pseudo-instruction will cause the processor to enter debug mode, as if the
jd_de_b input
had been asserted.
This bit is qualified with DBCR0
EDM
, which must be set for FDB to take effect.
31 DR
CPU Debug Request Control Bit
This control bit is used to unconditionally request the CPU to enter the Debug Mode. The
CPU will indicate that Debug Mode has been entered via the data scanned out in the shift-
IR state.
0 – No Debug Mode request
1 – Unconditional Debug Mode request
When the DR bit is set the processor will enter Debug mode at the next instruction
boundary.
1. Unused by Z0Hn2p
Table 470. OnCE Control Register Bit Definitions (continued)
Bit(s) Name Description
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