RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 859/936
e200z0h also defines two new debug events (CIRPT, CRET) for debugging around critical
interrupts.
In addition, e200z0h implements the Debug APU, which when enabled allows Debug
Interrupts to utilize a dedicated set of save/restore registers (DSRR0, DSRR1) for saving
state information when a Debug Interrupt occurs, and for restoring this state information at
the end of a debug interrupt handler by means of the se_rfdi instruction.
The e200z0h also provides the capability of sharing resources between hardware and
software debuggers. See Section 36.9.4, “Sharing Debug Resources by
Software/Hardware.
36.9.3 Hardware Debug Facilities
The e200z0h core contains facilities that allow for external test and debugging. A modified
IEEE 1149.1 control interface is used to communicate with the core resources. This
interface is implemented through a standard 1149.1 TAP (test access port) controller.
By using public instructions, the external debugger can freeze or halt the e200z0h core,
read and write internal state and debug facilities, single-step instructions, and resume
normal execution.
Hardware Debug is enabled by setting the External Debug Mode enable bit in Debug
Control register 0 (DBCR0
EDM
). Setting DBCR0
EDM
overrides the Internal Debug Mode
enable bit DBCR0
IDM
unless resources are provided back to software via the settings in
DBERC0. When the Hardware Debug facility is enabled, software is blocked from modifying
the “hardware-owned” debug facilities. In addition, since resources are “owned” by the
hardware debugger, inconsistent values may be present if software attempts to read
“hardware-owned” debug-related resources.
When hardware debug is enabled by setting DBCR0
EDM
=1, the registers and resources
described in Section 36.11, “Debug Registers are reserved for use by the external
debugger. The same events described in Section 36.10, “Software Debug Events and
Exceptions are also used for external debugging, but exceptions are not generated to
running software. Debug events enabled in the respective DBCR[0-2] registers are recorded
in the DBSR regardless of MSR
DE
, and no debug interrupts are generated unless a
resource is granted back to software via DBERC0 settings. Instead, the CPU will enter
debug mode when an enabled event causes a DBSR bit to become set. DBCR0
EDM
and
DBERC0 may only be written through the OnCE port.
Access to most debug resources (registers) requires that the CPU clock (m_clk) be running
in order to perform write accesses from the external hardware debugger.
36.9.4 Sharing Debug Resources by Software/Hardware
Debug resources may be shared by a hardware debugger and software debug based on the
settings of debug control register DBERC0. When DBCR0
EDM
is set, DBERC0 settings
determine which debug resources are allocated to software and which resources remain
under exclusive hardware control. Software-owned resources which set DBSR bits when
DBCR0
IDM
=1 will cause a debug interrupt to occur when enabled with MSR
DE
. Hardware-
owned resources which set DBSR bits when DBCR0
EDM
=1 will cause an entry into debug
mode. DBERC0 is read-only by software. When resource sharing is enabled,
(DBCR0
EDM
=1 and DBERC0
IDM
=1), only software-owned resources may be modified by
software, and all status bits associated with hardware-owned resources will be forced to ‘0’
in DBSR when read by software via a mfspr instruction. Hardware always has full access to
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