Nexus Development Interface (NDI) RM0046
860/936 Doc ID 16912 Rev 5
all registers and all register fields through the OnCE register access mechanism, and it is up
to the debug firmware to properly implement modifications to these registers with read-
modify-write operations to implement any control sharing with software. Settings in DBERC0
should be considered by the debug firmware in order to preserve software settings of control
and status registers as appropriate when hardware modifications to the debug registers is
performed.
Simultaneous Hardware and Software Debug Event Handing
Since it is possible that a hardware “owned” resource can produce a debug event in
conjunction with a software-owned resource producing a different debug event
simultaneously, a priority ordering mechanism is implemented which guarantees that the
hardware event is handled as soon as possible, while preserving the recognition of the
software event. The CPU will give highest priority to the software event initially in order to
reach a recoverable boundary, and then will give highest priority to the hardware event in
order to enter debug mode as near the point of event occurrence as possible. This is
implemented by allowing software exception handing to begin internal to the CPU and to
reach the point where the current program counter and MSR values have been saved into
DSRR0/1, and the new PC pointing to the debug interrupt handler, along with the new MSR
updates. At this point, hardware priority takes over, and the CPU enters debug mode.
Figure 505 shows the e200z0h debug resources.
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