RM0046 Clock Description
Doc ID 16912 Rev 5 97/936
Safety Port clock domains
The Safety Port module has two distinct software-controlled clock domains. The first clock
domain (Module Clock) is always supplied from the SP_PLL_CLK. The source for the
second clock domain (Protocol Clock) can either be the SP_PLL_CLK or the XOSC_CLK.
The user must ensure that the frequency of the first clock domain (Module Clock) clocked
from the MC_PLL_CLK is always the same or greater than the clock selected for the second
clock domain (Protocol Clock).
4.4 Clock behavior in STOP and HALT mode
In this section the term “resume” is used to describe the transition from STOP and HALT
mode back to a RUN mode.
The SPC560P40/34 supports the STOP and the HALT modes. These two modes allow to
put the device into a power saving mode with the configuration options defined in the ME
module.
The following constraints are applied on SPC560P40/34 to guarantee that in all modes of
operation a resume from STOP or HALT mode is always possible without the need to reset:
● STOP and HALT mode:
– SIUL clock is not gateable
– SIUL filter for external interrupt capable pins is always clocked with IRC
– Resume via interrupt that can be generated by any peripheral that clock is not
gated
– Resume via NMI
pin is always possible if once enabled after reset (no software
configuration that could block resume afterwards)
● STOP mode:
– IRC can NOT be switched off
– The System Clock Selector 0 is switched to the IRC and therefore the SYS_CLK is
feed by the IRC signal
– Resume via external interrupt pin is always possible (if not masked)
● HALT mode:
– The output of the System Clock Selector 0 can only be switched to a running clock
input
– Resume via external interrupt pin is always possible (if not masked) and IRC is not
switched off
4.5 System clock functional safety
This section shows the SPC560P40/34 modules used to detect clock failures:
● The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and
the XOSC signal against the IRC and provides clock out of range information about the
monitored clock signals.
● FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent
to the CGM module.
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