Nexus Development Interface (NDI) RM0046
866/936 Doc ID 16912 Rev 5
Instruction Address Compare event, a Linked Data Address Compare debug event occurs.
This event can occur and be recorded in DBSR regardless of the setting of MSR
DE
. The
normal DAC1 and DAC2 status bits in the DBSR are used for recording these events. The
IAC1 and IAC3 status bits are not set if the corresponding Instruction Address Compare
register is linked.
Linking is enabled using control bits in DBCR2.
Note: Linked DAC events will not be recorded if a load multiple word or store multiple word
instruction is interrupted prior to completion by a critical input or external input interrupt.
36.10.4 Trap Debug Event
A Trap debug event (TRAP) occurs if Trap debug events are enabled (DBCR0
TRAP
=1), a
Trap instruction (tw) is executed, and the conditions specified by the instruction for the trap
are met. This event can occur and be recorded in DBSR regardless of the setting of MSR
DE
.
When a Trap debug event occurs, the DBSR
TRAP
bit is set to ‘1’ to record the debug
exception.
36.10.5 Branch Taken Debug Event
A Branch Taken debug event (BRT) occurs if Branch Taken debug events are enabled
(DBCR0
BRT
=1) and execution is attempted of a branch instruction which will be taken (either
an unconditional branch, or a conditional branch whose branch condition is true), and
MSR
DE
=1 or DBCR0
EDM
=1. Branch Taken debug events are not recognized if MSR
DE
=0
and DBCR0
EDM
=0 at the time of execution of the branch instruction and thus DBSR
IDE
can
not be set by a Branch Taken debug event. When a Branch Taken debug event is
recognized, the DBSR
BRT
bit is set to ‘1’ to record the debug exception, and the address of
the branch instruction will be recorded in DSRR0.
36.10.6 Instruction Complete Debug Event
An Instruction Complete debug event (ICMP) occurs if Instruction Complete debug events
are enabled (DBCR0
ICMP
=1), execution of any instruction is completed, and MSR
DE
=1 or
DBCR0
EDM
=1. If execution of an instruction is suppressed due to the instruction causing
some other exception which is enabled to generate an interrupt, then the attempted
execution of that instruction does not cause an Instruction Complete debug event. The sc
instruction does not fall into the category of an instruction whose execution is suppressed,
since the instruction actually executes and then generates a System Call interrupt. In this
case, the Instruction Complete debug exception will also be set. When an Instruction
Complete debug event is recognized, DBSR
ICMP
is set to ‘1’ to record the debug exception
and the address of the next instruction to be executed will be recorded in DSRR0.
Instruction Complete debug events are not recognized if MSR
DE
=0 and DBCR0
EDM
=0 at
the time of execution of the instruction, thus DBSR
IDE
is not generally set by an ICMP debug
event.
Note: Instruction complete debug events are not generated by the execution of an instruction
which sets MSR
DE
to ‘1’ while DBCR0
ICMP
=1, nor by the execution of an instruction which
sets DBCR0
ICMP
to ‘1’ while MSR
DE
=1 or DBCR0
EDM
=1.
36.10.7 Interrupt Taken Debug Event
An Interrupt Taken debug event (IRPT) occurs if Interrupt Taken debug events are enabled
(DBCR0
IRPT
=1) and a non-critical interrupt occurs. Only non-critical class interrupts cause
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