RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 905/936
Figure 519. CPU Scan Chain Register (CPUSCR)
Instruction Register (IR)
The Instruction Register (IR) provides a mechanism for controlling the debug session by
serving as a means for forcing in selected instructions, and then causing them to be
executed in a controlled manner by the debug control block. The opcode of the next
instruction to be executed when entering debug mode is contained in this register when the
scan-out of this chain begins. This value should be saved for later restoration if continuation
of the normal instruction stream is desired.
On scan-in, in preparation for exiting debug mode, this register is filled with an instruction
opcode selected by debug control software. By selecting appropriate instructions and
controlling the execution of those instructions, the results of execution may be used to
examine or change memory locations and processor registers. The debug control module
external to the processor core will control execution by providing a single-step capability.
Once the debug session is complete and normal processing is to be resumed, this register
may be loaded with the value originally scanned out.
TDO
TDI
TCK
MSR
WBBR
high
32
32
031
031
PC
32
031
IR
32
031
CTL
32
031
WBBR
low
32
031
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