RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 297/936
Table 123. EEGR field descriptions
Field Description
2
FRC1BI
Force RAM Continuous 1-Bit Data Inversions
0 No RAM continuous 1-bit data inversions generated
1 1-bit data inversions in the RAM continuously generated
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
This bit can only be set if the same input enable signal (as that used to enable single-bit correction
reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory
corrections is always enabled.
3
FR11BI
Force RAM One 1-bit Data Inversion
0 No RAM single 1-bit data inversion generated
1 One 1-bit data inversion in the RAM generated
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit
position specified in ERRBIT[6:0], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same input enable signal (as that used to enable single-bit correction
reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory
corrections is always enabled.
6
FRCNCI
Force RAM Continuous Non-Correctable Data Inversions
0 No RAM continuous 2-bit data inversions generated
1 2-bit data inversions in the RAM continuously generated
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous non-correctable data inversion, it must
be cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
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