eTimer RM0046
728/936 Doc ID 16912 Rev 5
Table 384. DREQn field descriptions
Field Description
DREQn_EN
DMA Request Enable
Use these bits to enable each of the four module level DMA request outputs. Program the DREQ
fields prior to setting the corresponding enable bit. Clearing this enable bit will remove the request
but wíll not clear the flag that is causing the request.
1 = DMA request enabled.
0 = DMA request disabled.
DREQn
DMA Request Select
Use these fields to select which DMA request source will be muxed onto one of the two module
level DMA request outputs. Make sure each of the DREQ registers is programmed with a different
value else a single DMA source will cause multiple DMA requests. Enable a DMA request in the
channel specific INTDMA register after the DREQ registers are programmed.
00000Channel 0 CAPT1 DMA read request
00001Channel 0 CAPT2 DMA read request
00010 Channel 0 CMPLD1 DMA write request
00011 Channel 0 CMPLD2 DMA write request
00100 Channel 1 CAPT1 DMA read request
00101 Channel 1 CAPT2 DMA read request
00110 Channel 1 CMPLD1 DMA write request
00111 Channel 1 CMPLD2 DMA write request
01000 Channel 2 CAPT1 DMA read request
01001 Channel 2 CAPT2 DMA read request
01010 Channel 2 CMPLD1 DMA write request
01011 Channel 2 CMPLD2 DMA write request
01100 Channel 3 CAPT1 DMA read request
01101 Channel 3 CAPT2 DMA read request
01110 Channel 3 CMPLD1 DMA write request
01111 Channel 3 CMPLD2 DMA write request
10000 Channel 4 CAPT1 DMA read request
10001 Channel 4 CAPT2 DMA read request
10010 Channel 4 CMPLD1 DMA write request
10011 Channel 4 CMPLD2 DMA write request
10100 Channel 5 CAPT1 DMA read request
10101 Channel 5 CAPT2 DMA read request
10110 Channel 5 CMPLD1 DMA write request
10111 Channel 5 CMPLD2 DMA write request
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